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Operating Modes
Mode 4 (internal clock): TRM = 1 first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
N
Counter
0
N
N+1
M
N+ 1
Next 0-to-1 edge
TCR
TIO pin
TCF (Compare Interrupt if TCIE = 1)
width being measured
M
on TIO starts
counter from current
count and process
repeats. Overflow
may occur (TOF = 1).
Interrupt Servic e
reads TCR for
accumulated width
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO
of M - N clock periods.
stops the counter and loads TCR with the count.
Figure 9-12. Pulse Width Measurement Mode, TRM = 0
9.3.2.2 Measurement Input Period (Mode 5)
Bit Settings
Mode Characteristics
TC3
0
TC2
1
TC1
0
TC0
1
Mode
5
Name
Input period
Function
Measurement
TIO
Input
Clock
Internal
In Mode 5, the timer counts the period between the reception of signal edges of the same polarity
across the TIO signal. The value of the INV bit determines whether the period is measured
between consecutive low-to-high (0 to 1) transitions of TIO or between consecutive high-to-low
(1 to 0) transitions of TIO . If INV is set, high-to-low signal transitions are selected. If INV is
cleared, low-to-high signal transitions are selected. After the first appropriate transition occurs on
the TIO input signal, the counter is loaded with the TLR value. On the next signal transition of the
same polarity that occurs on TIO , TCSR[TCF] is set, and a compare interrupt is generated if the
TCSR[TCIE] bit is set. The contents of the counter load into the TCR. The TCR then contains the
value of the time that elapsed between the two signal transitions on the TIO signal. After the
second signal transition, if the TCSR[TRM] bit is set, the TCSR[TE] bit is set to clear the counter
and enable the timer. The counter is repeatedly loaded and incremented until the timer is
disabled. If the TCSR[TRM] bit is cleared, the counter continues to increment until it overflows.
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
9-13
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